1. Field of the Invention
This invention relates in general to means and methods for semiconductor devices and, more particularly to means and methods for partially dielectrically isolated, self-aligned, semiconductor devices.
2. Background Art
As semiconductor devices become smaller and are packed more tightly on a common substrate, parasitic leakage currents and parasitic capacitances associated with junction isolation regions have an increasingly adverse effect on device and circuit performance. Accordingly, there is an increasing need for dielectrically isolated devices.
In the prior art, dielectrically isolated (DIC) devices were formed by first etching a mesh shaped pattern of grooves in the upper surface of a single crystal semiconductor substrate so as to leave islands of single crystal material between the grooves, coating the grooves and the exposed islands with a dielectric layer, covering the dielectric layer with a thick polycrystalline layer, and then grinding away the single crystal substrate so as to expose the islands of single crystal material. This provided a structure in which each single crystal island was surrounded by a dielectric region embedded in a polycrystalline matrix. Individual devices could then be fabricated in the individual single crystal semiconductor islands. While this arrangement was satisfactory for building low density integrated circuits, particularly radiation hardened integrated circuits, it has not proved well suited to high density and large scale integrated circuits.
More recently, dielectrically isolated circuits have been prepared by taking a single crystal substrate, blanket implanting a very high dose of oxygen at an energy sufficient to place the peak of the implanted oxygen distribution well below the substrate surface. The implanted oxygen forms a thin buried dielectric layer. The implanted substrate is heated so as to anneal, in so far as possible, the structural damage in the single crystal semiconductor region between the surface and the implanted dielectric layer.
While this approach has permitted higher density circuits to be fabricated, it suffers from a number of significant disadvantages. For example, the very high implant doses required to form the buried insulating layer cause substantial crystal damage in the overlying single crystal region. Even after annealing, the dislocation densities are extremely high. These dislocations create undesirable parasitic leakage currents that degrade device and circuit performance. Further, when MOS devices are fabricated in the single crystal layer above the buried dielectric region, it is extremely difficult to provide a backgate bias contact to the individual devices since the prior art buried dielectric region extends under the gate and channel region as well as under the contacts. This makes it difficult or impossible to use the body effect to vary device performance.
Thus, there is a continuing need for improved means and methods for fabricating dielectrically isolated devices. Accordingly, it is an objective of the present invention to provide an improved means and method for dielectrically isolated devices where the dielectric isolation region extends under the terminals or contact portion of the device but not under the active regions.
It is an additional objective of the present invention to provide an improved means and method for dielectrically isolated MOS devices where the implanted dielectric isolation region is provided under the source and drain regions but not under the channel region.
It is a further objective of the present invention to provide an improved means and method for dielectrically isolated devices that provides self-aligned source, drain, and gate regions while avoiding implant damage under the gate region.
It is an additional objective of the present invention to provide an improved means and method for dielectrically isolated MOS devices where a common body contact can be maintained to the MOS channel regions through a conductive substrate.
It is a further objective of the present invention to provide an improved means and method for dielectrically isolated MOS devices wherein the gate dielectric and/or the channel region are protected from direct implanted damage during formation of the buried dielectric isolation layer.